An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network

Johnson, A.P., Halliday, D.M., Millard, A.G., Tyrrell, A.M., Timmis, Jonathan, Liu, J., Harkin, J., McDaid, L. and Karim, S. (2017) An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network. In: 2016 IEEE Symposium Series on Computational Intelligence (SSCI). UNSPECIFIED. ISBN 9781509042401

Full text not available from this repository.

Search Google Scholar

Abstract

The human brain is structured with the capacity to repair itself. This plasticity of the brain has motivated researchers to develop systems which have similar capabilities of fault tolerance and self-repair. Recent research findings have proven that interactions between astrocytes and neurons can actuate brain-like self-repair in a bidirectionally coupled astrocyte-neuron system. This paper presents a hardware realization of the bio-inspired self-repair architecture on an FPGA. We also introduce a reduced architecture for an FPGA-based hardware-efficient fault-tolerant system. This is based on the principle of retrograde signaling in an astrocyte-neuron network by simplifying the calcium dynamics within the astrocyte. The hardware optimized implementation shows more than a 90% decrease in hardware utilization and proves an efficient implementation for a large-scale astrocyte-neuron network. An Average spike rate of 0:027 spikes per clock cycle were observed for both the proposed models of astrocytes in the case of 100% partial fault.

Item Type: Book Section
Subjects: Computing > Artificial Intelligence
Computing
Engineering
Divisions: Faculty of Technology > School of Computer Science
Depositing User: Jonathan Timmis
Date Deposited: 27 Feb 2020 14:28
Last Modified: 27 Feb 2020 14:28
URI: http://sure.sunderland.ac.uk/id/eprint/11572

Actions (login required)

View Item View Item