A design-flow for high-level synthesis and resource estimation of reconfigurable architectures

Pasha, Muhammad Adeel, Siddiqui, Bilal and Farooq, Umer (2015) A design-flow for high-level synthesis and resource estimation of reconfigurable architectures. In: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 21 – 23 Apr 2015, Napoli, Italy.

More Information

Depositing User: Umer Farooq

Identifiers

Item ID: 16370

URI: http://sure.sunderland.ac.uk/id/eprint/16370

Official URL: https://ieeexplore.ieee.org/xpl/conhome/7118811/pr...

Users with ORCIDS

ORCID for Umer Farooq: orcid.org/0000-0002-5220-4908

Catalogue record

Date Deposited: 23 Aug 2023 15:33

Last Modified: 23 Aug 2023 15:33

Contributors

Author:	Umer Farooq
Author:	Muhammad Adeel Pasha
Author:	Bilal Siddiqui

University Divisions

Faculty of Technology > School of Engineering

Subjects

Engineering > Electrical Engineering

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